1. Field of the Invention
The present invention relates in general to a memory test system. In particular, the present invention relates to a memory test structure comprising memory built-in self-test circuits to reduce the peak power consumption of tested memories.
2. Description of the Related Art
Memory components must be tested for Wafer Acceptance (WAT). Currently, memories with memory built-in self-test (MBIST) circuits are tested on Automated Test Equipment (ATE), the major advantage of that test efficiency is not determined by test floorplans and test environments. In all kinds of integrated circuits, using the BIST circuit to test memory can reduce the complexity of the test process. With the wide use of BIST circuits, complex test requirements are no longer required. Thus, using BIST circuits to test memory can reduce test costs.
The peak power consumption of multiple concurrent tested memory built-in self-test (MBIST) memories is quiet large. During large peak power consumption, it is easy to misjudge the test result because power supplied by an exterior source is not enough to provide peak power consumption.